The invention pertains to a method of checking for races in a digital design. More particularly, the invention pertains to an efficient and accurate method of locating races within a very large scale integrated (VLSI) circuit comprising only one system clock.
The performance of VLSI circuits has been significantly improved in recent years. Many of their improvements are derived from new hardware devices which are capable of operating at higher clock frequencies. However, as the clock frequencies of such circuits are increased, increased efforts must be made to prevent performance degradation as a result of clock skew, edge degradation, and the like.
Clock skew is demonstrated in FIG. 2. Overlapping clock signals CK1 204 and CK2 206 may be ideally timed as illustrated by the dashed lines in FIG. 2. However, their timings, upon reaching a particular unit of a hypothetical VLSI circuit, may be as shown by the solid lines 200, 202 of FIG. 2. By design, the clock signals 204, 206 have an overlap designated by the left-most arrow 208. However, routing paths, manufacturing variances, and other factors can result in one or both of the clock signals being delayed before reaching a particular unit of the hypothetical VLSI circuit. These delays are known as clock skew. In FIG. 2, signal CK1 200 is "skewed", resulting in an additional overlap 210 between signals CK1 and CK2.
Another problem caused by manufacturing variances, line coupling, and other factors is edge degradation. Edge degradation is demonstrated in FIG. 3. If edge degradation is significant, clock signal edges may rise and fall slowly (demonstrated by the waveforms of clocks CK1N 300 and CK2N 302 in FIG. 3). In a high frequency circuit, these slow transitions from "clock HI" to "clock LO", or vice versa, can cause errors in a circuit pipeline (e.g., 1100, FIG. 11). Note that ideally, clock signals CK1N 304 and CK2N 306 are non-overlapping, but due to edge degradation, an overlap 308 between the signals can result.
Errors caused by clock skew and/or edge degradation are herein referred to as clock signal races and are characterized by data from one stage 1104 of a pipeline being passed to a subsequent stage 1114 before the proper clocking signal has been received to clear the subsequent stage 1114 of data previously stored in that stage.
Thus, a race may lead to a data collision and result in lost and/or corrupted data. As known to those skilled in the art, approximately 99% of all races are attributable to clock skew, and the slower rise/fall times of clock signal edges due to edge degradation.
Fortunately, clock races may be fixed using various "gated" clock signals. Examples of gated signals are disclosed in U.S. Pat. No. 5,124,572 to Mason et al., and U.S. Pat. No. 5,306,962 to Lamb, which are hereby incorporated by reference for all that they disclose. Gated clock signals are also disclosed in the U.S. Pat. Application of Perez filed Mar. 1, 1996 (Ser. No. 08/609,592) entitled "High-Performance, Low-Skew Clocking Scheme for Single-Phase, High-Frequency Global VLSI Processor Clocks", and the U.S. Patent Application of Naffziger filed Mar. 1, 1996 (Ser. No. 08/609,306) entitled "Local CMOS Clock Buffer Circuits". These applications are also incorporated by reference for all that they disclose. Mason et al. and Lamb disclose a clocking methodology for VLSI circuits which selectively uses the edges of two overlapping clocks and two non-overlapping clocks to eliminate race conditions. The overlapping clocks are used wherever possible to provide superior timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers.
However, before one may fix a race, one must first identify where race specifications have been violated. Existing methods which are used to induce and/or identify races include: inspection, varying clock inputs, and asserting top level signals.
Inspection relies on one or more engineers making a visual inspection of a circuit's schematic. Circuits are checked, and then cross-checked. This method is not only time consuming, but also error prone and non-exhaustive.
One method of inducing races involves creating a model of the circuit, and then varying the timing of the model's clock inputs. A disadvantage of this method is that it relies on the existence of more than one system clock.
Races are often identified by asserting top level signals. This method relies on induced race failures propagating to the "top" of a circuit (i.e., its input/output (I/O) ports, or contact pads). Unfortunately, many races do not propagate to the top. Of the races that do propagate to the top, a large percentage of the races may have a root cause which lies significantly distant from a top level signal. Failures must be traced to their root cause, and some races can be extremely difficult to debug. Furthermore, there is a problem of masking. When relying on a race to propagate to the top, one race can often mask the affects of another race. Such an occurrence can lead to numerous repetitions of the method, and complex, repetitive tracings through circuit paths.
Some of the newer VLSI circuits have only one system clock, and existing methods of race checking are ill-equipped to deal with these circuits. Race checking by inspection is obviously difficult due to the inherent complexity of VLSI circuits. Likewise, signal assertion is a less than adequate method since once a failure is identified, a race must be traced to its root cause through multiple stages of logic. This can be an extremely time consuming, costly, and unbearable task.
Varying clock signals to induce races is not even an option with a circuit having only one system clock. In such a circuit, overlapping and non-overlapping clocks are locally generated by each unit of a VLSI circuit. Variation of the single system clock input, from which all other clock signals are derived, fails to create the varying degrees of clock overlap which help to induce races.
Regardless of the method(s) used to check for races, it is very important to locate all races prior to building a silicon prototype. If races are not identified "pre-silicon", locating and debugging races becomes significantly more time consuming and costly.
It is therefore a primary object of this invention to provide an exhaustive method of checking for clock-based races.
It is another primary object of this invention to provide a method which more precisely pinpoints the location of races, thereby decreasing the time and effort required to debug them.
It is also an object of this invention to provide a method which increases the observability of races.
It is yet another object of this invention to provide a method which decreases the occurrence of race checking oversights and/or errors.
It is a further object of this invention to provide a method which may be used to identify races prior to the creation of circuit masks and/or a silicon prototype.
An additional object of this invention is to provide a method which can be used to locate races in a VLSI circuit having only one system clock.
A final object of this invention is to provide a method which can be used to detect races which do not propagate to the "top".